Generally, in a manufacturing process of a semiconductor device, the physical structure and electric characteristics of elements such as a transistor deviate from design values. Such deviation is called manufacturing variability. It is important to take the manufacturing variability into consideration in processes of circuit design and verification, in order to guarantee a normal operation of the manufactured semiconductor device.
For example, in general static timing analysis (STA), timing analysis is carried out by using a delay value in a corner condition (the worst condition). In other words, a margin according to the manufacturing variability is taken into consideration. By designing a circuit for timing constraints to be satisfied even under the corner condition, a delay due to the manufacturing variability can be absorbed. On the other hand, the design time increases to design a circuit for the timing constraint to be satisfied even under the corner condition.
Patent Literature 1 (Japanese Patent Publication (JP 2007-258569A)) describes a technique to reduce load impressed to a designer of a semiconductor device. Specifically, a level of manufacturing variability to be considered in a design step is lowered lower than that in case of a general design. After the semiconductor device is actually produced, a voltage and temperature are measured when a target delay is attained in the semiconductor device. Then, the measured voltage and temperature are shown to a user of the semiconductor device. In this case, the operation range of the semiconductor device is limited in advance but the load impressed on the designer can be reduced.
Also, in the field of the semiconductor device, the saving of a power consumption amount is one of the important problems. As the technique to reduce the power consumption amount in the semiconductor device, DVFS (Dynamic Voltage and Frequency Scaling) and AVS (Adaptive Voltage Scaling) are known.
DVFS is a system in which the power consumption amount is controlled by dynamically switching a voltage and/or a clock frequency in a circuit to be controlled. The voltage and the clock frequency are related to each other and the clock frequency needs to be lowered if the voltage becomes low. Oppositely, if the clock frequency is reduced in a range that the normal operation is guaranteed, the voltage (i.e. a consumed power) can be made low in correspondence to the reduction of the clock frequency. From such a viewpoint, in DVFS, a plurality of combinations of the voltage and the clock frequency in the range that the semiconductor device can operate normally are provided as operation points (modes). By dynamically switching an operation point according to a task, the power consumption amount can be controlled. For example, the techniques relating to DVFS are described in Patent Literature 2 (U.S. Pat. No. 6,943,613) and Patent Literature 3 (U.S. Pat. No. 7,093,143).
AVS is a system in which a supply voltage is adaptively controlled in accordance with a state (load, power and so on) of a circuit to be controlled. For example, the techniques relating to AVS are described in Patent Literature 4 (US 2005/0225376A) and Patent Literature 5 (U.S. Pat. No. 6,967,522).
Citation List:
                [Patent Literature 1]: JP 2007-258569A        [Patent Literature 2]: U.S. Pat. No. 6,943,613        [Patent Literature 3]: U.S. Pat. No. 7,093,143        [Patent Literature 4]: US2005/0225376A        [Patent Literature 5]: U.S. Pat. No. 6,967,522        